Role: Hardware and Firmware Design

This project was an end-to-end design of a sensorless brushless ESC using the STM32F051 for micro-drone propulsion, built to understand and control every layer of the motor drive stack rather than relying on commercial BLHeli hardware. The controller targets lightweight 2S platforms and prioritises fast commutation, low electrical noise, and robust fault handling so that it can coexist with sensitive IMU and radio subsystems on a small airframe.

The goal is to integrate with a also self-made flight controller (STM32F765), to end up with a drone capable of autonomous flight, that is fully implemented on a single PCB, together with the IMU and radio transceiver. The PCB will act as a frame, allowing for fast and reliable reproduction without need of mechanical frames, of custom made drones capable of expanding beyond its existing capabilities. It will support ports for cameras, other sensors, and more, putting it above the Crazyflie alternative for single PCB drones.

Control Strategy and Firmware Architecture

The ESC uses six-step trapezoidal commutation with back-EMF zero-cross detection, following the architecture used in most racing drone ESCs. This approach was chosen over FOC because it significantly reduces computational load, firmware complexity, and code size, allowing the system to run on an STM32F051 while still achieving high electrical RPM. AM32 firmware was selected as the control stack due to its open-source toolchain, active development, and compatibility with custom hardware targets.

Microcontroller and Hardware Targeting

An STM32F051K8 was selected as the main controller to match AM32 reference designs while keeping flash, pin count, and package size minimal. The chip runs at 48 MHz using the PLL to maximise PWM resolution and ADC throughput. Hardware group B from the AM32 target matrix was implemented so that the firmware could be used with minimal modification, while still allowing custom telemetry and protection features.

The board includes full SWD access for development, but the layout also anticipates a Tag-Connect footprint for future revisions to eliminate bulky debug headers. Multiple debug LEDs were added to expose power rails, MCU status, and fault states, enabling rapid bring-up without an oscilloscope during early testing.

ESC schematic showing STM32F051, DRV8300 gate driver, current sensing, and fault routing

Power Stage and Gate Drive

The power stage uses a discrete three-phase MOSFET bridge driven by a DRV8300 triple half-bridge gate driver. Although the DRV8300 is electrically over-rated for a 2S system, it was chosen because it is widely used in AM32 reference hardware, inexpensive, and available in a hand-solderable TSSOP package. Using a single integrated three-phase driver reduces routing complexity and ensures matched propagation delays between phases.

MOSFET selection was based on a worst-case phase current of approximately 8 A with significant headroom for transient spikes and regenerative back-EMF. Devices with ≥40 V Vds, low Rds(on), and high pulsed current capability were chosen to reduce conduction losses and thermal rise. The layout places the MOSFETs, driver, and high-frequency decoupling capacitors in a tight loop to minimise parasitic inductance and ringing, which is critical for both efficiency and EMI control.

Current Sensing and Protection

Low-side shunt resistors measure phase current, amplified by an INA180 with a gain selected to keep the ADC input within safe limits while maintaining sensitivity at low throttle. An RC filter on the amplifier output attenuates high-frequency switching noise before sampling. The conditioned signal feeds both the ADC for telemetry and a hardware comparator that triggers the TIM1 break input if the current exceeds a defined threshold, providing cycle-level over-current protection.

Power Distribution and Bring-Up Strategy

All major rails, VBAT, 5 V, and 3.3 V, can be powered externally to allow staged testing of the MCU, gate driver, and power stage independently. This reduces the risk of catastrophic failure during initial firmware development. Reverse-polarity and inrush mitigation are planned for future revisions, along with TVS protection on the phase nodes.

Signal Interfaces and Telemetry

The ESC accepts standard PWM (D-Shot soon to be supported) input from a flight controller, routed to the AM32 communication pin defined for hardware group B.

PCB Layout Considerations

Two-layer ESC PCB with separated power and analog ground regions

The PCB was routed to keep high-current switching loops as short and symmetric as possible while isolating the analog sensing network. Gate traces are length-matched to avoid phase skew. The design also exposes test points for phase voltages, current sense outputs, and logic rails, enabling systematic validation of each subsystem. There is ground stitching as well.

Flashing and Validation Workflow

The STM32 is programmed with the AM32 bootloader via ST-Link, after which firmware updates and configuration are performed through a flight controller using the AM32 configurator. This mirrors the workflow of commercial ESCs and allows in-system tuning of parameters such as dead-time, timing advance, and protection thresholds.

Initial validation was performed by powering logic rails independently, confirming PWM generation, then enabling the gate driver without a motor to verify correct phase sequencing. Motor tests were introduced only after confirming proper behaviour.

Future Work

The current revision focuses on reliable implementation for 2S micro-air vehicles. The next iteration will explore field-oriented control to improve efficiency, acoustic noise, and low-speed torque, which will require faster current sampling, phase-aligned ADC triggering, and a higher performance MCU. Inline phase current sensing is also being considered to enable true torque control and more accurate observer-based estimation.

From a hardware perspective, the design will migrate toward a compact 4-in-1 ESC architecture to reduce wiring mass and improve power distribution on multi-rotor frames. This will require thermal coupling analysis, shared bulk capacitance sizing, and careful separation of high di/dt switching domains between channels. Additional protection features such as TVS diodes on phase nodes, reverse polarity protection, and controlled inrush limiting are planned to improve survivability during battery hot-plug events.

Debug and manufacturing improvements include replacing the SWD header with a Tag-Connect footprint, refining the ground strategy based on measured switching waveforms, and tuning the current-sense filter using oscilloscope captures from the physical board. These changes aim to transition the design from a bring-up prototype to a repeatable, flight-ready propulsion module.